1. Field of the Invention
The present invention relates to the production of semiconductor devices and in particular to the preparation of indium phosphide semiconductor substrates for use in the production of semiconductor devices using MOVPE techniques.
2. Related Art
MOVPE (Metal Organic Vapour Phase Epitaxy) is commonly used to grow a wide variety of semiconductor devices comprising multiple layers which require precise material composition and thickness. In some materials systems, virtually monolayer control can be achieved using MOVPE when switching from one compound to another which in some cases is essential for accurate, repeatable device fabrication. The achievable purity of deposited layers using MOVPE is potentially very high but can be affected by the purity of the starting products. As long as the starting products are not totally pure, device manufacturers have to take steps to avoid or counter the unpredictable effects that the impurities have on manufacturing processes, or suffer from reduced device yield.
It has been shown that epitaxially deposited III-V semiconductors commonly suffer from the presence of conductive interfacial layers at the substrate interface [1].
This phenomenon presents a particular problem to InP based field effect transistors (FETs) grown on Fe-doped InP substrates because it prevents pinch-off by providing a parallel conduction path that cannot be controlled by gate voltage. This also raises output conductance, device-to-device leakage and can add a parasitic capacitance affecting high frequency performance.
Conducting interfacial layers can have many origins, however, the strongest recent evidence indicates accumulation of Si atoms at the substrate/epitaxial layer interface to be the major culprit [1]. Interfacial impurities have been variously attributed to out diffusion from the substrate, residues from substrate preparation solutions and contamination from ambient air. In addition, the inventors have observed Si accumulation in an MOVPE kit for several weeks following refurbishment of the vent-run gas switching manifold. Even when below detection limits in grown layers, this is another potential source of surface contamination during wafer heat-up. In practice, it is quite likely that several of these mechanisms may contribute to contamination simultaneously, varying in degree of severity depending on factors such as the substrate batch or manufacturer, its handling and preparation procedure, chemical batches and the history of the growth kit.
The significance of the accumulated silicon greatly increases as device complexity increases, since fabrication times increase giving the silicon more time to accumulate. Therefore, the production of highly integrated monolithic semiconductors including, for example, HFET (heterojunction field effect transistors), lasers and transmitters, HEMTs (high electron mobility transistors) and OEICs (opto-electronic integrated circuits) has highlighted the need to overcome the problem.
Many workers have developed processes for mitigating parallel conduction in FETs and HEMTs. Recently, H. Ishikawa et al in "Origin of n-type conduction at the interface between epitaxial-grown layer and InP substrate and its suppression by heating in phosphine atmosphere", J. Appl. Phys 71(8), 15 April 1992, pp 3898-3903, described a study into the origins of n-type conduction due to Si atoms at the epitaxial layer-substrate interface. In the study Ishikawa et al theorised that Si atoms originated in the air, possibly from the filters used in clean rooms, and became adsorbed into the InP. The adsorbed Si subsequently accumulated at the epitaxial layer-substrate interface and manifested itself as n-type impurities causing n-type conduction at the boundary. To counter this, Ishikawa et al proposed a method of removing the atoms from the InP substrate by annealing it in a PH.sub.3 atmosphere, The process involved heating the InP to a temperature of around 700.degree. C. for 20 minutes with a PH.sub.3 flow rate of 1200 sccm. The results indicated that a high proportion of the Si atoms adsorbed into the InP surface were desorbed, which reduced the effect of n-type Si conduction.
In another paper, "Highly Resistive Iron-doped AlInAs layers grown by Metalorganic Chemical Vapour Deposition", J. Appl. Phys. Vol. 31 (1992) pp L376-L378, Ishikawa et al described a method of fabricating a semi-insulating iron-doped AlInAs buffer layer on an InP substrate prior to the deposition of further epitaxially-grown layers. By this method, the influence of the substrate itself, over the epitaxially-grown layers, is mitigated.
Although the existence of parallel conduction mechanisms has been recognised for at least 10 years, and more recently the causes of the mechanisms, for example n-type conduction by silicon atoms, have been isolated, surprisingly, none of the proposed methods of overcoming or countering the effects of the mechanisms have proved entirely satisfactory. In such a rapidly growing and important field as III-V semiconductor device fabrication, a method of successfully and reproducibly fabricating devices without parallel conduction mechanisms would be of extreme commercial importance.